Conventionally, a number of integrated circuits are formed on a single wafer. The wafer is scribed along unused channels between integrated circuits so that each integrated circuit can be broken off, or otherwise separated, from the wafer. Finally, each integrated circuit is individually packed in an integrated circuit package.
Generally, the integrated circuits are tested before the wafers are broken and also following the packaging. Important tests that the integrated circuits typically have to pass following the packaging include delay tests, which are designed to verify that the circuits perform at the desired speed. Indeed, the ICs should operate at a clock frequency as determined in their specifications.
As a general trend, with the evolution of IC technology, the time delays of the integrated circuits decrease, which means that the propagation time of the pulses get smaller, resulting in a need for ever more precise, and most of all faster, measurements testers for performing time delay tests.
Several methods are commonly employed for testing the speed of integrated circuits. One such method consists in testing the functionalities of the circuits at the highest frequency they can tolerate. However, this approach involves the use of high-speed testers, which are expensive devices that must be frequently replaced as the IC technology evolves.
Built-in self-test methods are commonly developed for testing integrated circuits comprising embedded memory. Such methods provide testing facilities included by design into the circuits. However, since they result in larger surfaces of circuits and require additional sophisticated tools, such methods are not as often used with circuits comprising logic circuitry.
Integrated circuits comprising logic circuitry such as those using complementary metal oxide semiconductor (CMOS) logic circuitry are widely used in the fabrication of microprocessors, application specific integrated circuits (“ASICs”) and memory storage areas.
Generally stated, the CMOS technology involves connecting p-channel MOS (for “metal oxide semiconductor”) transistor networks and n-channel MOS transistor networks together into a MOS or IC device. The resulting devices, referred to as CMOS, are characterized by a decreased static dissipation of power, since they require very little current to operate in their steady state. Indeed, CMOS circuits only require power when their state is altered. CMOS are thus especially useful in the field of battery powered portable devices.
However, it is a shared concern in the art that the packaging step of ICs adds considerably to their manufacturing cost. Efforts have therefore been made in order to increase the level of testing ICs while they are still on the wafer, before even proceeding to the packaging step.
There is obviously room for improvement in the art, in relation to means for simply and cost effectively performing delay tests while the ICs are still on the wafer.